1. Field
Example embodiments relate to a hybrid interconnect structure and an electronic device employing the same, and more particularly, to a hybrid interconnect structure employing graphene and an electronic device employing the same.
2. Description of the Related Art
Efforts for reducing a line width or thickness of metal wiring to be used for relatively high-density and relatively high-performance semiconductor devices are being conducted. The number of semiconductor chips integrated for each wafer may increase by reducing a line width or thickness of the metal wiring. In addition, when the thickness of metal wiring is reduced, a capacitance of a line may be reduced, thereby increasing the speed of a signal through the wiring.
However, when a line width or thickness of metal wiring is reduced, resistance increases, and thus, a decrease in resistance of a wiring structure is desirable. A current interconnect technique is approaching a physical limitation region in which a specific resistance increases according to a decrease in line width and thickness.